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A3992 DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Features and Benefits
1.5 A, 50 V continuous output rating Low RDS(on) DMOS output drivers Short-to-ground protection Shorted load protection Optimized microstepping via six bit linear DACs Programmable mixed, fast, and slow current decay modes 4 MHz internal oscillator for digital timing Serial interface controls chip functions Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Inputs compatible with 5 or 3.3 V control signals Sleep and Idle modes
Description
Designed for pulse width modulated (PWM) current control of bipolar microstepped stepper motors, the A3992 is capable of continuous output currents to 1.5 A and operating voltages to 50 V. Internal fixed off-time PWM current control timing circuitry can be programmed via the serial interface to operate in slow, fast, or mixed decay modes. The desired load current level is set via the serial port with two six bit linear DACs in conjunction with a reference voltage. The six bits of control allow maximum flexibility in torque control for a variety of step methods, from microstepping to full step drive. Load current is set in 1.56% increments of the maximum value. Synchronous rectification circuitry allows the load current to flow through the low RDS(on) of the DMOS output driver during current decay. This feature eliminates the need for external clamp diodes in most applications, saving cost and external component count, while minimizing power dissipation. Internal circuit protection includes short-to-ground, shorted load, thermal shutdown with hysteresis, and crossover current protection. Special power up sequencing is not required. The A3992 is supplied in a thin profile (1.2 mm maximum height) 24 pin TSSOP (suffix LP) with exposed thermal pad and a 24 pin plastic DIP with dual copper batwing tabs (suffix B). The exposed thermal pad on the LP is at ground potential and needs no electrical isolation. Both packages are lead (Pb) free with 100% matte tin leadframe plating.
Packages
24 pin batwing DIP (suffix B) and 24 pin TSSOP with exposed thermal pad (suffix LP)
LP package approximate scale
Typical Application
0.22 F VREG 10 F 5 k Microcontroller or Controller Logic ROSC CLOCK DATA STROBE REF SLEEP VDD
0.22 F CP1 CP2 VCP 0.22 F
VBB1
A3992
VBB2 OUT1A OUT1B SENSE1
100 F
0.1 F OUT2A OUT2B SENSE2 0.1 F
3992DS
A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Selection Guide
15 pieces/tube 62 pieces/tube Tape, 4000 pieces/reel *Contact Allegro for additional packing options
Part Number A3992SB-T A3992SLP-T A3992SLPTR-T
Packing*
Package
24 pin batwing DIP 24 pin TSSOP with exposed thermal pad
Absolute Maximum Ratings
Characteristic Load Supply Voltage Output Current Logic Supply Voltage Logic Input Voltage Range VBBx to OUTx Voltage OUTx to SENSEx Voltage REF Reference Voltage SENSE Voltage (dc) Operating Ambient Temperature Maximum Junction Temperature Storage Temperature VREF VSENSE TA TJ(max) Tstg Range S Symbol VBB IOUT VDD VIN Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. Notes Rating 50 1.5 7.0 -0.3 to VDD + 0.3 50 50 3 500 -20 to 85 150 -55 to 150 Units V A V V V V V mV C C C
Thermal Characteristics*
Characteristic Symbol Notes B package on 4-layer PCB B package on 2-layer PCB with 3.15 in.2 2 oz. copper each side LP package on 4-layer PCB LP package on 2-layer PCB with 3.8 in.2 2 oz. copper each side *Additional thermal data available on the Allegro website. Rating 26 36 28 32 Units C/W C/W C/W C/W
Package Thermal Resistance
RJA
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Functional Block Diagram
0.22 F
0.22 F
VREG 2V VDD UVLO and Fault Detect Regulator Bandgap
CP2
CP1
Charge Pump
VCP
MUX 0.22 F
To VDD
6 Bit Linear DAC
VCP
DMOS Full Bridge 1
VBB1 >47 F
Internal Oscillator OSC OSC Select/ Divider
OUT1A Programmable PWM Timer Fixed-Off Blank Mixed Decay Gate Drive OUT1B
SENSE1
OCP
CLOCK To VDD DATA STROBE SLEEP Serial Port
Control Logic Phase 1,2 Sync Rect Mode Sync Rect Disable Mode 1, 2 DMOS Full Bridge 2 VBB2
OUT2A OUT2B Programmable PWM Timer To 2V VREF Fixed-Off Blank Mixed Decay Buffer 6 Bit Linear DAC
SENSE2
0.1 F
REF
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
ELECTRICAL CHARACTERISTICS1 valid at TA= 25C, VBB = 50 V, fPWM < 50 kHz, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ.2 Max. Units Output Drivers Operating, IOUT = 1.5 A 15 - 50 V Load Supply Voltage Range VBB During Sleep mode 0 - 50 V VOUT = VBB - <1.0 50 A Output Leakage Current IDSS - <-1.0 -50 A VOUT = 0 V Source driver, IOUT = -1.5 A - 0.54 0.6 Output On Resistance RDS(on) Sink driver, IOUT = 1.5 A - 0.54 0.6 Source diode, IF = -1.5 A - - 1.2 V Body Diode Forward Voltage VF Sink diode, IF = 1.5 A - - 1.2 V fPWM < 50 kHz - - 8 mA Motor Supply Current IBB Operating, outputs disabled - - 6 mA Sleep or Idle mode - - 20 A fPWM < 50 kHz - - 12 mA Outputs off - - 10 mA Logic Supply Current IDD Idle mode (Word 1, D18 = 0) - - 1.5 mA Sleep mode - - 100 A Control Logic Logic Supply Voltage Range VDD Operating 4.5 5 5.5 V VIN(1) 2.0 - - V Logic Input Voltage VIN(0) - - 0.8 V IIN(1) VIN = 2.0 V - <1.0 20 A Logic Input Current IIN(0) VIN = 0.8 V - <-2.0 -20 A Input Hysteresis 0.20 - 0.40 V >2 - - s Minimum sleep pulse width tS OSC input frequency fOSC(in) Divide by 1 (Word 2, D13=0, D14=1) 2.5 - 6 MHz OSC input duty cycle 40 - 60 % OSC shorted to GND 3 4 5 MHz Internal Oscillator fOSC ROSC= 51 k 3.4 4 4.6 MHz DAC Accuracy VDAC Measured relative to REF buffer output - 0.5 - LSB Reference Input Voltage Range .5 - 2.6 V Reference Buffer Offset VOS - 10 - mV Word 0, D18 = 0, D17 = 1, VREF = 0.5 to 2.6 V 7.4 8 8.8 - Reference Divider Ratio VREF/VSENSE 3.6 4 4.4 - Word 0, D18 = 1, D17 = 1, VREF =0.5 to 2.6 V Reference Input Current IREF VREF = 2.0 V -0.5 - 0.5 A 1.940 2.0 2.060 V Internal Reference Voltage VREFINT Comparator Input Offset Volt. VIO VREF = 0 V -5 0 5 mV Internal VREF, Range = 8, DAC = 63 -6 0 6 % Internal VREF, Range = 8, DAC = 31 -9 0 9 % 3 GM Error VERR -6 0 6 % Internal VREF, Range = 4, DAC = 63 Internal VREF, Range = 4, DAC = 15 -10 0 10 % 50% to 90%; PWM change to source on 500 800 1000 ns 50% to 90%; PWM change to source off 35 - 250 ns Propagation Delay Times tpd 50% to 90%; PWM change to sink on 500 800 1000 ns 50% to 90%; PWM change to sink off 35 - 250 ns Crossover Dead Time tDT 300 650 900 ns UVLO Enable Threshold VUVLO VDD rising 3.9 4.2 4.45 V UVLO Hysteresis VUVLOHYS 0.05 0.10 - V Protection Circuitry Overcurrent Protection Threshold4 IOCPST 2 - - A Overcurrent Blanking tOCP 1 - 3 s Thermal Shutdown Temperature TJ - 165 - C Thermal Shutdown Hysteresis TJHYS - 15 - C 1Negative current is defined as coming out of (sourcing) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF / Range) - VSENSE ] / (VREF / Range). 4OCP is tested at T = 25C in a restricted range and guaranteed by characterization. A
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Serial Interface Description
D7 - 12 Bridge 2 Linear DAC. 6 bit word to set the
The A3992 is controlled via a 3 wire serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is written as two 19 bit words, 1 bit to select which word (referred to here as Word 0 and Word 1) and 18 bits of data. The serial port is defined in the following tables and text descriptions.
Word 0 Bit Assignments
desired current level for bridge 2. Setting all bits to zero disables Full Bridge 2, all drivers off. (See Current Regulation in the Functional Description section.) D13 Bridge 1 Phase. This bit controls the direction of current for motor phase 1 as defined below:
D13 0 1 OUT1A L H OUT1B H L
Word 0 is selected by setting D0 = 0. Assignments are summarized in the following table, and desribed in detail in the remainder of this section.
Word 0 Bit Assignments Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Function Word Select = 0 Bridge 1, DAC, LSB Bridge 1, DAC, Bit2 Bridge 1, DAC, Bit3 Bridge 1, DAC, Bit4 Bridge 1, DAC, Bit 5 Bridge 1, DAC, MSB Bridge 2, DAC, LSB Bridge 2, DAC, Bit2 Bridge 2, DAC, Bit3 Bridge 2, DAC, Bit4 Bridge 2, DAC, Bit 5 Bridge 2, DAC, MSB Bridge 1 Phase Bridge 2 Phase Bridge 1 Mode Bridge 2 Mode Reference Select Range Select
D14 Bridge 2 Phase. This bit controls the direction of current for motor phase 2 as defined below:
D14 0 1 OUT2A L H OUT2B H L
D15 Bridge 1 Mode. This bit determines the decay
for Full Bridge 1 as defined below:
D15 0 1 Mode Mixed Decay Slow Decay
D16 Bridge 2 Mode. This bit determines the decay
for Full Bridge 2 as defined below:
D16 0 1 Mode Mixed Decay Slow Decay
D17 Ref Select. This bit determines the reference
input for the two 6 bit linear DACs. Logic low selects internal 2 V reference voltage, logic high selects external reference input on the REF pin.
D18 Gm Range Select. D18 determines if the scaling
D1 - D6 Bridge 1, Linear DAC. 6 bit word to set de-
factor used is 4 or 8:
D18 0 1 Divider /8 /4 Load Current ITRIP = VDAC/(RSENSE x 8) ITRIP = VDAC/(RSENSE x 4)
sired current level for bridge 1. Setting all bits to zero disables Full Bridge 1, all drivers off. (See Current Regulation in the Functional Description section.)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
from erroneously resetting the source enable latch, the sense comparator is blanked. The blank timer runs after the off time counter to provide the programmable blanking function. The blank timer is reset when PHASE is changed.
D3 - D7 Fixed Off Time. 5 bits to set the fixed
Word 1 Bit Assignments
Word 1 is selected by setting D0 = 1. Assignments are summarized in the following table, and desribed in detail in the remainder of this section.
Word 1 Bit Assignments Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Function Word Select = 1 Blank Time LSB Blank Time MSB Off Time LSB Off Time Bit1 Off Time Bit2 Off Time Bit3 Off Time MSB Fast Decay Time LSB Fast Decay Time Bit1 Fast Decay Time Bit2 Fast Decay Time MSB C0 Oscillator Control C1 Oscillator Control SR Control Bit 1 SR Control Bit 2 Reserved for testing Reserved for testing Idle Mode
off-time for the internal PWM control circuitry. Fixed off-time is defined by: tOFF = (1 + n) x POSC x 8 - POSC , where n = 0 to 31. For example, with a master oscillator frequency of 4 MHz ( POSC = 250 ns), the fixed off-time is adjustable from 1.75 to 63.75 s, in increments of 2 s.
D8 - D11 Fast Decay Time. 4 bits to set the fast
decay portion of fixed off-time for the internal PWM control circuitry. The fast decay portion is defined by: tfd = (1 + n) x POSC x 8 - POSC , where n = 0 to 15. For example, with a master oscillator frequency of 4 MHz ( POSC = 250 ns), the fixed off-time is adjustable from 1.75 to 31.75 s, in increments of 2 s. For tfd > toff , the device will effectively operate in fast decay mode.
D12 - D13 Oscillator Control. 2 bits to set timing
D1 - D2 Blank Time. 2 bits to set the blank time scal-
options:
D13 0 0 1 1 D12 0 1 0 1 Source and Rate Internal clock 4 MHz External clock f / 1 External clock f / 2 External clock f / 4
ing factor for the current sense comparator:
D2 0 0 1 1 D1 0 1 0 1 Time 4 x POSC 6 x POSC 8 x POSC 12 x POSC
When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike
A 4 MHz internal oscillator can be used for the timing functions. If more precise control is required, an external oscillator can be input to OSC pin. To accommodate a wider range of system clocks, an internal divider is provided to generate the desired MO frequency.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
D16, D17 (Reserved). 2 bits reserved for testing.
D14 - D15 Synchronous Rectification. 2 bits set the
different modes of operation (see Synchronous Rectification in the Functional Description section):
D15 0 0 1 1 D14 0 1 0 1 Synchronous Rectifier Active Disabled Passive Allegro defined use
They should be programmed to 0 during normal operation. D18 Idle Mode. The device can be put into the lowpower Idle mode by writing a 0 to D18. The outputs are disabled, the charge pump turned off, and the device consumes a lower supply current. The undervoltage monitor circuit remains active.
Functional Description
VREG. The VREG pin should be decoupled with a
0.22 F capacitor to ground. This internally generated supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled.
Current Regulation. The reference voltage can be set
PWM signals to the control block. In mixed decay mode, the first portion of the off-time operates in fast decay, until the fast decay time count is reached, followed by slow decay for the remainder of the fixed off-time. If the fast decay time is set longer than the offtime, the device effectively operates in fast decay mode.
Oscillator. The PWM timer is based on an oscillator
by analog input to the REF terminal, or via the internal 2 V precision reference. The choice of reference voltage and selection of sense resistor set maximum trip current, as follows: ITRIPMAX = VREF / (Range x RSENSE) . Microstepping current levels are set according to the following equations: ITRIP = VDAC / (Range x RSENSE) , and VDAC = ((1+DAC) x VREF) / 64 , where DAC is the input code, 1 to 63 (Word 0, D1 to D12), and Range is 4 or 8, as selected by Word 0, D18. Programming a DAC input code to 0 disables the corresponding bridge, and results in minimum load current.
PWM Timer Function. The PWM timer is program-
input, typically 4 MHz. The A3992 can be configured to select either the 4 MHz internal oscillator or, if more precise accuracy is required, an external clock can be connected to the OSC terminal. If an external clock is used, 3 internal divider choices are selectable via the serial port to allow flexibility in choosing fOSC based on available system clocks. If the internal oscillator option is used, the absolute accuracy is dependent on process variation of resistance and capacitance. A precision resistor can be connected from the OSC terminal to VDD to further improve the tolerance. The frequency is calculated as: fOSC = 204 x 109 / ROSC
.
mable via the serial port to provide fixed off-time
If the internal oscillator is used without the external resistor the OSC terminal should be connected to GND.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Short to Ground. Should a motor winding short to
Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than VBBx to drive the source FET gates. A 0.22 F ceramic capacitor is required between CP1 and CP2 for pumping purposes. A 0.22 F ceramic capacitor is required between VCP and the VBB terminals to act as a reservoir to operate the high-side FETs. Sleep Mode. Control input on the SLEEP pin is used
to minimize power consumption when not the device is not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. Logic low puts the device into Sleep mode, logic high allows normal operation and startup of the device into the home position. When asserted low, the serial port is reset. All bits are reset to 0s, with the exception of D7, the fixed off-time MSB, which is set to 1. This prevents the off-time from being too short, which could result in a loss of current control. When coming out of Sleep mode, allow 1 ms before issuing a step command, to allow the charge pump to stabilize.
Shutdown. In the event of a fault due to excessive
ground, the current through the short will rise until the overcurrent (OCP) threshold is exceeded, a minimum of 2 A. The driver will turn off after a short propagation delay and latch the device. The device will remain latched until the SLEEP input goes high or VDD power is removed. As shown in panel A of the figure below, a short to ground will produce a single overcurrent event.
Shorted Load. During a shorted load event, the cur-
junction temperature, or to low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers and resets the data in the serial port.
rent path is through the sense resistor. The device will be protected, however, the device does not see this as a fault because the current path is not interrupted, so this condition will not latch the part. When a bridge turns on, the current will rise and exceed the overcurrent threshold. After a blank time of approximately 1s, the driver will look at the voltage on the SENSE pin. The voltage on the SENSE pin will be larger than the voltage set by the VREF pin, and the bridge will turn off for the time set by the OSC pin. Panel B of the figure below shows a shorted load condition with an off-time of 30 s. MUX. The MUX pin is reserved for Allegro internal use and has no function to the end user. In the application, this pin can be tied to ground or left floating.
Fault latched
toff = 30 s
2 A / div. 500 ns / div. (A) Short-to-ground event
2 A / div. 5 s / div. (B) Short-to-load event
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
with the two serial port control bits: 1. Active mode. Prevents reversal of load current. is triggered, by a bridge disable command or internal Turns off synchronous rectification when a 0 current fixed off-time cycle, load current recirculates accordlevel is detected. ing to the decay mode selected by control logic. The 2. Passive mode. Allows reversal of current, but will A3992 synchronous rectification feature turns on the turn off the synchronous rectifier circuit if the load appropriate MOSFETs during current decay, and effeccurrent inversion ramps up to the current limit. tively shorts out the body diodes with the low RDS(on) 3. Disabled. Prevents MOSFET switching during load driver. This lowers power dissipation significantly, and recirculation in fast decay portion of the off-time. Durcan eliminate the need for external Schottky diodes for ing the slow decay portion of the off-time, the low-side most applications. switch turns on, which recirculates current through the low-side MOSFET and low-side body diode. Three distinct modes of operation can be configured
Synchronous Rectification. When a PWM off-cycle
Applications Notes
Current Sensing. To minimize inaccuracies in sensThermal Protection. Circuitry turns off all drivers
ing the IPEAK current level caused by ground trace I*R drops, the sense resistor should have an independent ground return to the GND terminal of the device. For low value sense resistors, the I*R drops in the PCB sense resistor traces can be significant and should be taken into account. The use of sockets should be avoided because they can introduce variation in RSENSE due to their contact resistance. Allegro MicroSystems recommends a value of RSENSE given by: RSENSE = 0.5 / ITRIP MAX .
STROBE CLOCK DATA A SLEEP H C D
when the junction temperature reaches 165C typical. It is intended only to protect the device from failures due to excessive junction temperatures, and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C.
Serial Port Write Timing Operation. Data is clocked
into a shift register on the rising edge of a CLOCK signal. Normally, STROBE is held high, and is only brought low to initiate a write cycle. The data is written MSB first. Refer to the diagram below for timing requirements.
E F G
MSB B
LSB - D0
Serial Port Timing Diagram
A. Minimum Data Setup Time B. Minimum Data Hold Time C. Minimum Setup Strobe to Clock rising edge D. Minimum Clock High Pulse Width E. Minimum Clock Low Pulse Width 15 ns 10 ns 120 ns 40 ns 40 ns F. Minimum Setup Clock rising edge to Strobe G. Minimum Strobe Pulse Width H. Minimum Sleep to Clock Setup Time I. Setup "Idle" Release to Output Enable 50 ns 120 ns 50 s 1 ms
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
under the device, to serve both as a low impedance ground point and thermal path. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CVBB1) should be closer to the pins than the bulk capacitor (CVBB2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device.
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3992 must be soldered directly onto the board. On the underside of the A3992 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A3992, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout, shown in the diagram below, illustrates how to create a star ground
OUT1A
OUT1B
VBB
OUT1A GND CS1 RS1 U1
OUT1B VBB
CS1 RS1 1
SENSE1 OUT1A NC STROBE VBB1 NC OUT1B
A3992
PAD
CP2 CP1 VCP GND OSC SLEEP VREG OUT2B VBB2
CCP CVCP ROSC CVBB2 CREG
CCP
CLOCK
CVCP
DATA GND REF
CREF
CREF
MUX VDD OUT2A SENSE2
ROSC CVBB2 CVDD RS2 CS2 VREF OUT2A OUT2B
VREF
CS2
RS2
CVBB1
CREG
CVBB1
OUT2A
CVDD
OUT2B
LP package layout shown
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Device Pin-out Diagrams
B Package
VCP 1 CP1 2 CP2 3 OUT1B 4 VBB1 5 GND 6 GND 7 SENSE1 8 OUT1A 9 STROBE 10 CLOCK 11 DATA 12 24 OSC 23 SLEEP 22 VREG 21 OUT2B 20 VBB2 19 GND 18 GND 17 SENSE2 16 OUT2A 15 VDD 14 MUX 13 REF
LP Package
SENSE1 1 OUT1A 2 NC 3 STROBE 4 CLOCK 5 DATA 6 GND 7 REF 8 MUX 9 VDD 10 OUT2A 11 SENSE2 12 PAD 24 VBB1 23 NC 22 OUT1B 21 CP2 20 CP1 19 VCP 18 GND 17 OSC 16 SLEEP 15 VREG 14 OUT2B 13 VBB2
Terminal List Table Number B LP Package Package
1 2 3 4 5 6, 7, 18, 19 8 9 10 11 12 13 14 15 16 17 20 21 22 23 24 - - 19 20 21 22 24 7, 18 1 2 4 5 6 8 9 10 11 12 13 14 15 16 17 3, 23 -
Name
VCP CP1 CP2 OUT1B VBB1 GND SENSE1 OUT1A STROBE CLOCK DATA REF MUX VDD OUT2A SENSE2 VBB2 OUT2B VREG SLEEP OSC NC PAD
Pin Description
Reservoir capacitor terminal Charge pump capacitor terminal Charge pump capacitor terminal DMOS Full Bridge 1, output B Load supply Ground. On B package, internally fused to the die pad for enhanced thermal dissipation. Sense resistor terminal for Full Bridge 1 DMOS Full Bridge 1, output A Logic input Logic input Logic input Gm reference input Not used Logic supply DMOS Full Bridge 2, output A Sense resistor terminal for Full Bridge 2 Load supply DMOS Full Bridge 2, output B Internal regulator Logic input Oscillator input No connection Exposed thermal pad for enhanced thermal dissipation.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Package B, 24 Pin DIP with Fused Pins
1.280 32.51 1.230 31.24 24 19 18
A B
.014 0.36 .008 0.20
.280 7.11 .240 6.10 A 1 2 6 7
.300 .7.62
.430 10.92 MAX
.195 4.95 .115 2.92 .015 0.38 MIN .100 .2.54 .070 1.78 .045 1.14 24X .022 .056 .014 .036 .010 [0.25] M C .150 3.81 .115 2.92
.210 5.33 MAX
SEATING PLANE
C
.005 0.13 MIN
Preliminary dimensions, for reference only Dimensions in inches Metric dimensions (mm) in brackets, for reference only (reference JEDEC MS-001 AF) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Package LP, 24 Pin TSSOP with Exposed Thermal Pad
24 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MO-153 ADT) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 24X 0.10 [.004] C 24X 0.30 .012 0.19 .007 0.10 [.004] M C A B
7.9 7.7
.311 .303
A B
8 0 0.20 .008 0.09 .004
B
4.5 4.3
.177 .169 6.6 6.2 .260 .244
0.75 .030 0.45 .018 1 .039 REF
A
1
2 0.25 .010 SEATING PLANE 0.65 .026 1.20 .047 MAX 0.15 .006 0.00 .000 0.65 .026 NOM C SEATING PLANE GAUGE PLANE
0.45 .018 NOM
2X 0.20 .008 MIN C
3 .118 NOM
5.9 .232 NOM
1.85 .073 NOM
4.32 .170 NOM
22X 0.20 .008 MIN
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c) 2006, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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